1. Field of the Invention
Embodiments of the invention relate to semiconductor memory devices. More particularly, embodiments of the invention relate to semiconductor memory devices adapted to perform a burst operation accessing memory cells in response to sequentially generated internal addresses.
2. Description of the Related Art
Conventional semiconductor memory devices often include a normal cell array having a plurality of memory cells arranged in a matrix of rows and columns, and a redundant cell array having memory cells used to repair defective memory cells in the normal cell array. Many conventional semiconductor memory devices are also adapted to operate in so-called “burst mode.” Burst mode operations are generally characterized by accessing a plurality of data bits, the number of which is defined by a value termed “burst length,” in response to a single command.
FIG. 1 is a block diagram of a flash memory—one common type of conventional semiconductor memory device. Referring to FIG. 1, an address buffer 31 latches and buffers an external address EXADDR provided by an external input/output line or bus (I/O). Further, an address counter 35 generates a sequentially changing internal address INADDRi, based on a buffered address BADDR provided by the address buffer 31. A page buffer/Y-gate 13 associated with a normal cell array 11 is enabled in response to the internal address INADDRi decoded by an address decoding unit 40. A redundancy decider 51 activates a redundancy flag signal REDFL when the internal address INADDRi, which corresponds to an embedded address READDR, is generated.
A data input driver 61 receives data from a buffering input line BDI and provides it to either a normal input line NDI or a redundancy input line RDI in response to an input driving signal DICLK (e.g., a defined clock signal). In this case, the direction (e.g., NDI or RDI) to which the data apparent on the buffering input line BDI is driven is determined by the redundancy flag signal REDFL. In similar vein, a data output multiplexer (MUX) 63 receives data via a normal output line NDO or a redundancy output line RDO and provides the data to a multiplexing (muxing) output line MDO in response to the redundancy flag signal REDFL. In this case, the origin (e.g., NDO or RDO) of the data to be provided to the muxing output line MDO is determined by the redundancy flag signal REDFL.
A data latch buffer 65 provides data received from the external input/output line (I/O) to the buffering input line BDI. Further, the data latch buffer 65 latches data received from the muxing output line MDO, as well as an internal local output line LDO (not shown) in response to an output latch signal DLCLK2. Subsequently, this latched data is provided to the external input/output line (I/O) in response to a read enable signal /RE applied to control logic unit 80.
In fact, the control logic unit 80 receives externally provided and conventionally understood external control signals /CE, /RE, /WE, CLE, and ALE, and generates a plurality of internal control signals, including AICLK, XIA, CNCLK, DICLK, DLCLK1, DLCLK2 and SCON in response to one or more of the external control signals /CE, /RE, /WE, CLE and ALE. The operational timing of the exemplary semiconductor memory device shown in FIG. 1, as well as the relationship between the foregoing control signals will be described in some additional detail in relation to FIGS. 2 and 3 and relative to a data input mode and a data output mode.
In FIGS. 2 and 3, a burst mode operation (e.g., one continuously changing the column address) is illustrated. In this example, a column address at which the burst operation starts is assumed to be ADDR(N). As shown in FIG. 2 and with reference to FIG. 1, it is assumed that a redundant memory cell in the redundant cell array 21 is accessed, instead of a memory cell of the normal cell array 11 corresponding to a column address of ADDR(N+1). As shown in FIG. 3 and with reference to FIG. 1, it is further assumed that another redundant memory cell in the redundant cell array 21 is accessed, instead of a memory cell of the normal cell array 11 corresponding to a column address of ADDR(N+2).
Referring to FIGS. 2 and 3, at intervals p21 and p31 during which a command latch enable signal CLE is “activated” (i.e., transitions to a logically high (H) state or level, or “goes high”), a command controlling the operational mode of the semiconductor memory device is received. At intervals p22 and p32 during which an address latch enable signal ALE is activated, the external address EXADDR is latched by address buffer 31.
Thereafter, in the data input mode illustrated in FIG. 2, input data is stored in the page buffer 13 of the normal cell array 11, or in the page buffer 23 of the redundant cell array 21. Analogously, in the data output mode illustrated in FIG. 3, output data is latched in the page buffer 13 of the normal cell array 11, or in the page buffer 23 of the redundant cell array 21.
Thereafter, data from the memory cell of the normal cell array 11 corresponding to the internal address INADDRi decoded by the address decoding unit 40 is provided to the normal output line NDO, while data from the memory cell of redundant cell array 21 is provided to the redundancy output line RDO.
In the input mode illustrated in FIG. 2, the redundancy flag signal REDFL is activated in response to the internal address INADDRi generated as ADDR(N+1) at time t21. In response to the internal address INADDRi generated as ADDR(N+2), the redundancy flag signal REDFL is deactivated (i.e., transitions to a logically low (L) state or level, or “goes low”) at time t22. In the output mode illustrated in FIG. 3, the redundancy flag signal REDFL is activated in response to the internal address INADDRi generated as ADDR(N+2) at time t31, but deactivated in response to the internal address INADDRi generated as ADDR(N+3) at time t32.
When the operating frequency of the foregoing exemplary semiconductor memory device increases or when the operating voltage (e.g., VCC) supplied to thereto decreases, the response speed of the redundancy decider 51 will generally slow. In this case, the response margin associated with the redundancy flag signal REDFL will become markedly decreased.
Within the data input mode of the conventional semiconductor memory device, the response margin associated with the redundancy flag signal REDFL, as measured from the time the internal address INADDRi is generated, is limited to a period t21 of about ½ the clock cycle of the input driving signal DICLK. There is a problem in that, if the activation timing of redundancy flag signal REDFL lags, for example, from t21 to t21′ and from t22 to t22′, data D2 corresponding to the address ADDR(N+2), rather than data D1 corresponding to the address ADDR(N+1) will be driven onto the redundancy input line RDI at t23′ and t24′, etc.
Further, within the output mode of the conventional semiconductor memory device, data on the muxing output line MDO depends on the response speed of the redundancy flag signal REDFL. That is, if the response speed of the redundancy flag signal REDFL lags, for example, from t31 to t31′ and from t32 to t32′, the data transfer window assigned to data DO2 on the muxing output line MDO and corresponding to the address ADDR(N+3) will be compressed. In this case, there is a problem that data DO2 from the normal cell array 11, rather than data RDO from the redundant cell array 21, is latched in response to the clock of the output latch signal DLCLK2 corresponding to the address ADDR(N+2), and data RDO from the redundant cell array 21, rather than data DO3 from the normal cell array 11, is latched in response to the clock of the output latch signal DLCLK2 corresponding to the address ADDR(N+3). That is, the conventional semiconductor memory device is problematic in that the precision with which data is latched in response to the output latch signal DLCLK2 decreases.
Consequently, the conventional semiconductor memory device suffers from several problems associated with the response margin of the redundancy flag signal, as defined in relation to the generation timing of an internal address INADDRi.